Integrated circuit memories generally contain a two dimensional array of storage cells arranged in rows and columns. A common architecture connects all cells in a row to a common row line, often referred to as the "word line" and all cells in a column to a common column line often called the "digit line".
Cells in the array are identified by a binary row address and a binary column address. A row decoder responds to the binary row address and activates one row line for read or write access. A column decoder responds to the binary column address and activates read or write circuitry associated with one column, conventionally, a sense amplifier connected across a pair of complementary digit lines.
Integrated circuit memories are also generally binary logic circuits in which information is stored and transferred as logic states (conventionally, voltages) representing complementary logic values that are alternately referred to as "on" and "off", " true"and "false", "logic 1" and "logic 0", or logic "high" and logic "low". A voltage of 5 volts may represent the logic 1 state while a voltage of zero volts may represent the logic 0 state. Because of the constraints of resistance, capacitance, etc., the individual cells are usually at an intermediate voltage. Thus, subcircuits are associated with the digit lines of integrated circuit memories to pull the intermediate logic 1 voltage up to, or in excess of the full logic 1 voltage, for example, 5 volts. Other subcircuits pull the intermediate logic 0 down to, or below the logic 0 voltage, for example 0 volts. A common architecture employs a P-sense amplifier for the pull up subcircuit and an N-sense amplifier as the pull down subcircuit.
The present invention is particularly applicable to a conventional architecture used in dynamic random access memories (DRAM) and video random access memories (VRAM). In the conventional architecture each memory cell comprises a transistor and a capacitor connected in series. One side of the capacitor is connected to a reference voltage, and the other side is connected to the digit line through the transistor. The gate of the transistor is connected to the row line. Information is stored in the form of charge on the capacitor, which charge is input and output via the digit line and gated by the row line acting on the transistor gate. Often a large number of such cells are connected to each digit line. The digit lines are organized in pairs with an N-sense amplifier and a P-sense amplifier associated with each pair. The N-sense amplifier and the P-sense amplifier are each connected across a pair.
A sense amplifier is a bistable circuit having two complementary signal nodes (sense nodes) used for both input and output. In a read access, an addressed cell is gated onto the first digit line and no cells are gated onto the second digit line. The sense amplifier will then attain the bistable state corresponding to the charge of the addressed cell. The first and second digit lines will be driven by the sense amplifier to complementary states. In a write access a data signal, and its complement are gated onto a pair of digit lines with sufficient energy to overcome the sense amplifier's response to the addressed cell. The sense amplifier, after attaining the state corresponding to the data signal, will cause the addressed cell to be appropriately charged. When the read or write cycle is over, the pairs are shorted together (equilibrated), which quickly brings them to a mid-voltage level, resetting them for the next cycle.
A common arrangement of the various parts of the circuit described above locates the column decoder and DRAM input/output terminals at one end of the digit lines and the N-sense amplifiers at the center of the digit lines, thereby dividing each of the digit lines into two halves. One half of a digit line extends from the N-sense amplifier to the column decoder. The other half extends from the N-sense amplifier to the P-sense amplifier. In a conventional VRAM architecture the second half continues beyond the P-sense amplifier and connects to a sequential-access memory (SAM) port.
As is well-known, integrated circuit memories are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer. Each wafer is subsequently cut into hundreds of identical dies or chips. The advantages of building integrated circuits with smaller individual circuit elements are well known: more and more circuitry may be fabricated on a single chip, electronic equipment may become less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, circuit performance may improve and higher clock speeds become feasible. For integrated circuit memories there are some disadvantages. As the size of the individual cell is reduced, the size of the individual electrical components in the cell and the strength of the electrical signals associated with them is also reduced. As the number of individual storage cells on a single chip is increased, the length of the digit lines connecting cells to sense amplifiers becomes longer. The capacitance associated with each digit line becomes large in comparison to the capacitance of a memory cell. Hence, the signal transferred to the digit line from an individual storage cell becomes weaker and the time for developing a useful signal level on a digit line will increase. As is well known, speed is an important factor in such memories. The faster the cells can be written, the faster the associated computer circuit of which the memory may be a part can operate, and the more functions the computer can adequately perform.
A number of enhancements have been made to DRAM and VRAM architecture to increase the signal level and sense amplifier response time. Several such enhancements are described in U.S. Pat. Nos. 4,748,349 and 4,636,987 and co-pending application Ser. No. 07/931,929. The former patent describes a circuit which boosts the voltage on the row line and, thus, the gate of the gating transistors to a vague above the high logic voltage of the circuit. Boosting permits the full high logic voltage to be placed on the cell capacitor, since the threshold voltage drop across the gating transistor is eliminated. The latter patent describes an architecture in which an N-sense amplifier is connected to a pair of digit lines at the mid point. Each half digit line connects to the N-sense amplifier through an isolation transistor. The isolation transistors respond to a timing signal to isolate the N-sense amplifier from one half of the digit line pair during a read cycle. For example, when the row being addressed is on the left half of the digit line pair, the isolating transistors between the N-sense amplifier and the left half of the digit line pair are on while the isolating transistors between the N-sense amplifier and the right half are off. Thus, the N-sense amplifier is connected to only one half of the full digit line during the read cycle. During a write cycle the P-sense amplifier is turned off and input data signals are driven from the I/O lines onto the full length of the digit lines. Co-pending application Ser. No. 07/931,929 describes an isolation technique for faster read cycles. The method of writing data to a cell includes turning off the P-sense amplifier and driving input data from the I/O lines onto the full length of the digit lines.
There remains a need for a memory architecture that allows fast write cycles. A solution which also decreases power dissipation would be desirable. For many applications of integrated circuit memories, such as for portable computers and other battery powered intelligent devices, the amount of power available is limited. It is important in such applications that sense amplifiers not only are fast and small, but also consume a minimum of power. In the conventional technologies, the largest component of the total power used in a DRAM is used to charge and discharge digit lines.